1. Technical Field
The present disclosure relates to a memory controller and a storage device and the like that control to suppress degradation due to variation in a data holding characteristic and the number of times of rewriting of a nonvolatile memory.
2. Related Art
Conventionally, a semiconductor storage device such as an SD (Secure Digital) card as a card-type recording medium which incorporates therein a flash memory is extremely compact and extremely thin. Because of its easiness of handling, the semiconductor storage device is widely used to record data such as images in digital cameras and portable devices.
The flash memory incorporated in the semiconductor storage device is configured by many physical blocks of a fixed size, and can erase data in a unit of a physical block. To respond to recent demands for a larger capacity, multiple-value flash memories (MLC: Multi-Level Cell) that can accumulate data of two or more bits in one cell are commercialized as flash memories.
FIG. 1 shows an example of a relationship between a threshold voltage (Vth) and the number of electrons that are accumulated in a floating gate of a multiple-value flash memory. As shown in FIG. 1, in a four-value flash memory, an accumulation state of electrons in the floating gate is managed in four states in accordance with the threshold voltages (Vth). An erase state has a lowest potential, and this state is expressed as (1, 1). Along with accumulation of electrons, threshold voltages discretely increase, and these states are expressed as (1, 0), (0, 0), and (0, 1). Because threshold potentials increase in proportion to the number of accumulated electrons in this way, two-bit data can be recorded in one memory cell by controlling the threshold value to be settled at a predetermined potential.
However, in the multiple-value flash memory, because the four states are discriminated by a charge quantity of electrons, a difference of threshold voltages between the states is smaller than that of a two-value memory (SLC: Single Level Cell).
Further, when data rewriting is repeated each time the number of times of rewriting increases, a slight damage occurs in a gate oxide film by injection and extraction of electrons. When these damages are accumulated, many electron traps are formed. Therefore, the number of electrons accumulated in the actual floating gate decreases. Because the number of electrons accumulated in the floating gate becomes small in proportion to a finely divided semiconductor process, an influence of the electron traps becomes large.
In this way, in accordance with the multiple-value recording that supports a larger capacity of the flash memory and miniaturization of a semiconductor process, a problem of degradation in the data holding characteristic of the flash memory has become noticeable.
A first method for solving the above problem is to reinforce error correction. For example, error correction of a flash memory of 20n generation is based on 40-bit correction, and error correction of a flash memory of 10n generation is based on 60-bit correction.
A second method for solving the above problem is a method called leveling that equalizes the number of times of rewriting blocks of the flash memory. Leveling is a method of managing an address of the flash memory to convert a logical address as an interface with an outside into a physical address that is internally managed, and write data written in the same logical address into an actually different physical address. However, variation in the data holding characteristic of a cell of the flash memory cannot be shielded by the leveling.
In Japanese Unexamined Patent Publication No. 2006-18373, the following is proposed. In a flash memory configured by a plurality of chips, blocks in mutually different chips of the flash memory are associated, and the associated plurality of blocks are handled as a common group. Then, by allocating one block in a group to a block for parity of user data written in other block in the corresponding group, an error correction capacity is reinforced, thereby suppressing degradation in the data holding characteristic of the flash memory.
As described above, the required number of error corrections following the miniaturization of a semiconductor process tends to increase. Therefore, there are commercialized flash memories such as an error-free NAND that incorporates an error correction function in the flash memory itself and a Management-NAND that accesses by a logical address, not only by the error correcting access, and internally averages the numbers of times of rewriting.
Although error correction policies of the error-free NAND and the Management-NAND are not fixed, in performing error correction of a maximum number of bits, there is a very small possibility that throughput of a maximum interface speed of the flash memory is satisfied. This is because an error correction algorithm employed by error correction of a BCH code and the like becomes the following (P1), (P2).
(P1) Possibility of error correction and decision of the number of correction bits
(P2) Detection and correction of error correction position
To achieve the (P2), a method of repeatedly performing error correction of few bits by considering an installation area and power consumption is often employed.
In the Management-NAND, because management of a flash memory is internally performed, data reading is performed by issuing a read command using a read-prefix logical address and the number of sectors to be read as arguments. When a reading error occurs, this is notified by an interruption signal or the like. Therefore, success of read operation can be known only in a read command unit.
A problem when the Management-NAND is used instead of a flash memory in the configuration of Japanese Unexamined Patent Publication No. 2006-18373, for example, is described below.
By using five Management-NANDs, user data is written into four Management-NANDs, and parity data of the user data is written into one Management-NAND. The parity data is generated by calculating EXOR of 4-byte user data extracted from each Management-NAND.
FIG. 2 is a view showing assignment of logical sectors and Management-NANDs. In FIG. 2, M0, M1, M2, M3, M4 respectively denote Management-NANDs having a capacity of 2 MB. Into a Management-NAND (M0), sector0, sector4, . . . , sector4092 are written. Into a Management-NAND (M1), sector1, sector5, . . . , sector4093 are written. Into a Management-NAND (M2), sector2, sector6, . . . , sector4094 are written. Into a Management-NAND (M3), sector3, sector7, . . . sector4095 are written. Into a Management-NAND (M4), Parity sector0, Parity sector1, Parity . . . , sector1023 are written. In this case, Parity sector0 denotes 512-byte parity data generated by calculating EXOR of user data of sector0, sector1, sector2, sector3. Similarly, Parity sector1 denotes 512-byte parity data generated by calculating EXOR of user data of sector4, sector5, sector6, sector7. Parity sector1023 denotes 512-byte parity data generated by calculating EXOR of user data of sector4092, sector4093, sector4094, sector4095.
In the case of reading data from a memory card in which the data is written in this way, there is a following problem. Data is read from the Management-NAND by issuing a read command using a read-prefix logical address and the number of sectors to be read as arguments. When a reading error occurs, the reading error is notified by an interruption signal or the like. Therefore, success of read operation can be known only in a read command unit.
According to the above method, in a read command of 4 Kbytes, for example, when an error occurs after reading first 2 Kbytes and an interruption occurs, a read command for reading only the latter 2 Kbytes needs to be issued to obtain data of the latter 2 Kbyte data. Further, when a reading error occurs in the first 512 bytes of the latter 2 Kbytes, a read command of an address of next 512 bytes needs to be issued. Therefore, a processing time at the time of occurrence of an error becomes large. As a result, at a position where a reading error occurs in video data reproduction, a transfer rate drops extremely, and omission of a video frame and the like occurs.
When a read command is issued in each Management-NAND in a sector unit to avoid the above operation, a process becomes simple, but a command overhead becomes large. Therefore, a transfer rate when an error does not occur drops.